1. Field of the Invention
The present invention relates to a dual storage node pixel for a CMOS sensor. In particular, the invention relates to use of the two storage nodes for subtraction of background illumination.
2. Description of Related Art
In a conventional CMOS imager, a photo generated signal in a pixel is integrated for a period of time and then subsequently read out. Generally, in some sensors, a single frame (an array of pixels) is collected and then read out before the collection of the subsequent frame. Also, in other sensors, a single frame (an array of pixels) is collected during an integration period that overlaps a period where the previously collected frame of pixels is being read out. There may be some disadvantages that arise from the time delay between collecting two frames of data.
For example, for smart air bag deployment, at the moment of a crash, a decision must be made whether to deploy an airbag and, if so, with what force. This decision must be made in <10 ms with unknown and changing scene lighting. To capture an image with varying light conditions, a standard CMOS image sensor requires one exposure with a pulsed light emitting diode (LED) source, one frame readout, a second exposure without the LED, a second frame readout, and finally off-chip subtraction to form a difference image, the difference image being the illuminated image with the background illumination subtracted out. Any change in lighting during the 1 millisecond or more interval between exposures creates image artifacts disrupting pattern recognition.
For example, in a 40 mile per hour crash where the occupant continues to move at 40 miles per hour relative to a car frame mounted camera, a 1 millisecond image delay represents an occupant movement of over 17 millimeters. On the other hand, if the time interval between the two images were to be reduced to 10 microsecond, the movement would be less than 0.18 millimeters.
Shyh-Yih Ma and Liang-Gee Chen, describe a basic charge transfer pixel but without most of the architectural and clocking improvements described in this improvement. See Shyh-Yih Ma and Liang-Gee Chen, A Single-Chip CMOS APS Camera with Direct Frame Difference Output, IEEE J. Solid State Circuits, vol. 34, no. 10, pp. 1415-1418, 1999. Stacy Kamasz, et al., describe a dual node CCD pixel in U.S. Pat. No. 5,585,652, titled Method and Apparatus for Real-Time Background Illumination Subtraction. 